CS 631-02 Systems Foundations — Meeting Summary¶

Quick Recap¶

The session reviewed core operating system concepts, focusing on process isolation and virtual memory, led by Professor Greg. Key topics included:

The three ingredients for process isolation: processor modes, interrupts (especially timer interrupts), and page tables.
How multi-level page tables work on 32-bit and 64-bit systems, including the role of the RISC-V satp register.
A tour of the OctX kernel code, covering page-table walking and memory mapping.
Introduction to Project 6: implementing a “track” program to instrument and collect system call and memory usage metrics from user-level processes, supported by new system calls for enabling tracking and extracting data.

Greg:
Review Project 6 test cases (especially around ls) to ensure the autograder behaves as expected.
Collaboration:
Students: Send any scoring issues via a single private post to Greg and Shreyas (instructor and TA). Consolidate all issues in one message.
Greg and Shreyas: Review and resolve reported scoring issues within the next few days.
Students: Complete Project 6 (tracking program) by next Thursday.
Note: Students were also told to send score complaints to Greg, which duplicates the first item above.

Two submission issues were announced:
Duplicate repositories with a “-01” suffix.
A scoring regression.
Action: Students should report any scoring problems via a single private post to the instructor and TA.
The instructor will spend the next few days resolving technical issues and noted a delay in updates due to a Canvas configuration oversight.
The session transitioned into a review of virtual memory and the OctX kernel’s page tables to prepare for Project 6 (due next Thursday).

Early PCs (e.g., IBM PC with MS-DOS) had limited support for concurrency and process isolation.
Effective process isolation requires:
Processor modes (kernel vs. user).
Interrupts (notably timer interrupts for preemption).
Virtual memory.
Early 8-bit processors often lacked sufficient interrupt sophistication, leading operating systems to rely on cooperative multitasking (applications voluntarily yielding control).

Page tables multiplex memory across processes and isolate address spaces.
Benefits:
Prevents unauthorized access to other processes’ memory and kernel memory.
Overhead exists but is small relative to protection benefits on modern processors.
Historical alternatives (e.g., type-safe languages, systems like Unity) were discussed, but conventional virtual memory with page tables remains dominant.

Multi-level page tables reduce memory overhead by allocating lower-level tables only where needed.
Example (32-bit concept):
Splitting a 20-bit page number into 10-bit L1 and 10-bit L0 indices reduces a flat 4 MB table to 4 KB per allocated L0 table.
Higher-level entries for unmapped regions remain unused.

Page-table walking:
The processor indexes L1, then L0 to locate the physical page frame.
Page Table Entries (PTEs) are zeroed by default; a mapping is valid only when the valid bit is set.
Translation Lookaside Buffer (TLB):
Caches recent virtual-to-physical translations to avoid frequent page-table walks.

Fully associative caches and TLBs help achieve high hit rates alongside virtual memory.
Three pillars of modern isolation and security:
Processor modes
Interrupts
Page tables
Side-channel risks were introduced through a light-switch-and-bulb analogy (observing indirect signals to infer hidden state), setting the stage for later discussion.

Modern CPUs with speculative execution can be vulnerable to cache-based side channels (e.g., Meltdown, Spectre).
Attackers may infer data across protection boundaries by timing memory accesses.
While mitigations exist, complete elimination is impractical. Even browser-based JavaScript can be a vector under some conditions.

64-bit schemes discussed with a focus on RISC-V’s SV39 (three-level page tables), as used in OctX/Octos.
PTE fields:
Valid bit
Read/Write/Execute permissions
Accessed and Dirty bits (used by the OS for memory management policies)
The satp register controls the active page table and is switched between user and kernel address spaces as needed.

Kernel page table initialization and mapping:
The kernel constructs its page table and uses a map function to create mappings.
The kernel virtual address space includes reserved I/O regions and maps kernel code around the 2 GB region with appropriate permissions.
Trampoline page:
Facilitates safe transitions between user and kernel modes during system calls.
Page table walking:
A walk function mirrors hardware page-table traversal to retrieve or construct PTEs when needed.

A new kernel feature collects runtime metrics:
System call counts
Bytes read and written
Memory usage (text, heap, stack)
Demonstrated using ls:
Tracking does not alter program behavior; it instruments kernel paths to gather metrics.
Output will be used for reporting and grading in Project 6.

Two new system calls were introduced for Project 6:
track_self: Enables tracking for the calling process.
track_wait: Retrieves/aggregates tracking data, typically after the tracked process completes.
Reporting requirements:
System call counts
Total bytes read/written
Memory usage details (text, heap, stack)
Guidance:
Instrument kernel code paths carefully to ensure accurate metrics.
Match autograder specifications precisely.
Additional details on virtual memory and address spaces will be covered in the next session (Thursday).