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CS 631-02 Systems Foundations — Meeting Summary

  • Date: Mar 24, 2026
  • Time: 02:51 PM Pacific Time (US and Canada)
  • Meeting ID: 882 2309 0019

Quick Recap

The session covered Project 2 wrap-up and an introduction to RISC-V machine code and tooling:

  • Introduced the Docker-based RISC-V development environment, enabling consistent builds and execution across platforms.
  • Reviewed 32-bit RISC-V instruction formats and components (opcode, register selectors, func3, func7).
  • Demonstrated manual decoding of instruction words and a simple emulator that reads machine code from memory.
  • Showed debugging support using GDB within the containerized environment.
  • Discussed workflow with Cargo for running and testing RISC-V applications.

Next Steps

Instructor (Greg)

  • Release Project 3 specification and requirements (today or tomorrow).
  • Update guides with links to RISC-V reference materials and resources.
  • Add debugging support files to the in-class repo:
  • Dockerfile
  • Makefile
  • RISC-V debug script
  • GDB init
  • Test and document the RISC-V debug script on Beagle machines; update docs as needed.
  • Consider adding GDB TUI mode configuration (optional).
  • Investigate configuring .cargo to allow cargo run to use QEMU, per student request.
  • Provide deeper notes on the emulator structure during Thursday’s session.

Students

  • Pull the latest in-class repo for updated notes, example code, and debugging support files.
  • Incorporate the provided Rust program and the subprocess/command that invokes GCC into the NT-Lang binary generation process (as specified).
  • Optionally bring the new debugging support files into personal project repos.

Note: Action items are assigned to Greg (instructor) or to students where implied by the transcript.

Summary

RISC-V Project Planning

  • The upcoming project is due Thursday at 11:59.
  • The plan progresses from RISC-V machine code basics to ISA details, leading into Project 3: building a RISC-V emulator.
  • Updated project guidelines and reference links will be provided. Emphasis was placed on the open-source RISC-V specifications.
  • Docker-based development now includes GDB debugging support.

RISC-V Container System Implementation

  • The run system supports:
  • Native execution on RISC-V 64-bit hosts (e.g., Beagle machines).
  • Emulation via QEMU inside containers.
  • A demonstration showed expression evaluation and generated assembly (e.g., stack-based operations to compute A0 × 3).
  • Project components:
  • RISC-V assembly programming.
  • Extending T-Lang from Project 1, with a near-term focus on augmenting expression mode to handle command-line arguments.

NT-Lang Command-Line Extension

  • Goal: Pre-populate environments with command-line arguments without modifying the tree interpreter.
  • NTLANG-C compilation flow:
  • The compiler generates foo.s by combining static and generated code.
  • The final line references the code generation function label.
  • Assignment: Translate the C version into RISC-V assembly, including:
  • Stack allocation for an array.
  • Initialization and argument parsing.
  • Invocation of the code generation function.

CodeGen Implementation

  • In main.s, include a specific label: CodeGen_func_S after the return statement.
  • Generated code will be produced by walking the tree, using a stack-machine-like approach (similar to Java/Python bytecode).
  • Discussion covered zero-initializing registers; while not required, it may aid in diagnosing codegen issues.
  • A Rust NT-Lang program will be included to generate the binary and invoke GCC.

RISC-V Container Support Details

  • The system runs either natively on Beagles or inside a container:
  • Containers use a specialized RISC-V 64-bit GCC toolchain.
  • Native systems use the host’s GCC as appropriate.
  • Overview of container technology:
  • Containers provide a standardized cross-build environment.
  • Tools include Docker and OrbStack.

Docker and RISC-V Tooling

  • Containers vs. virtual machines:
  • Containers are lightweight and share the host kernel.
  • VMs emulate full systems and are heavier.
  • Demonstrated a Docker container with Ubuntu and RISC-V tools.
  • Updates include:
  • Dockerfile and Makefile improvements.
  • GDB init for debugging.
  • After a short break, the class continued with machine code and binary formats.

AI Coding Tools — Feature Testing

  • A feature tested on Beagles worked correctly.
  • Discussion covered:
  • Cursor’s containerized environments with headless browsers and UI recording (subscription required).
  • Cloud Code’s dispatch feature, which appears to run locally rather than in the cloud.

Machine Code and Assembly

  • Processors execute binary; assembly is a human-readable abstraction.
  • For this emulator, focus is on 32-bit instruction words (despite GCC supporting 16-bit compressed forms).
  • Assembly is easier to parse than high-level languages due to a lack of recursive structures.
  • Demonstrations included:
  • Hex-to-binary conversion.
  • Using objdump to view assembly.
  • A RISC-V resources page will be added to the guides.

32-bit Instruction Formats

  • Opcode determines instruction format.
  • R-type:
  • Uses func3 and func7 to identify operations (e.g., add, sll).
  • I-type:
  • Includes a 12-bit immediate along with register operands.
  • The I-type discussion was cut off at the end of the transcript.

Instruction Encoding Limitations

  • 12-bit immediates constrain the representable range.
  • RISC-V was contrasted with x86’s variable-length instructions, with RISC-V favored for simplicity.
  • Manual decoding examples demonstrated extracting opcode, register selectors, and function fields to identify instruction types and operations (e.g., add vs. sub).

Rust: Assembly and Emulation Basics

  • Demonstrated setting a function pointer to assembly and dereferencing with unsafe in Rust.
  • Showed extracting opcode fields using bit masks.
  • Introduced handling of instruction types (R-type, I-type) in the emulator.

Rust: Machine Code Inspection

  • Demonstrated reading instruction words directly from memory instead of calling functions.
  • Used the RISC-V debug script in a container:
  • Set breakpoints.
  • Inspected register values during execution.
  • Announced:
  • Completion of Project 2.
  • Imminent release of Project 3 specifications.
  • A deeper emulator-structure discussion planned for Thursday.
  • Clarified cargo run vs. cargo test:
  • cargo run can auto-select the appropriate target based on the operating system.