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CS 631-01 Systems Foundations — Meeting Summary

Date: Apr 02, 2026
Time: 08:12 AM Pacific (US and Canada)
Meeting ID: 870 0988 0761

Quick Recap

  • The session introduced combinational logic and digital circuits, explaining how analog voltages (0–5V) are mapped to digital values (0 and 1).
  • The three foundational gates—AND, OR, and NOT—and their Boolean algebra representations were covered.
  • A one-bit full adder was built using the sum-of-products method derived from a truth table.
  • The instructor demonstrated translating truth tables into circuits using the Digital software tool and showed how to compose a 4-bit ripple-carry adder through abstraction and component reuse.
  • The class concluded with an introduction to sequential logic and latches; more detail will follow next session along with a lab on schematic entry and circuit simulation.

Next Steps

  • Share meeting notes with students and post formal notes on the course website. (Greg)
  • Provide a download/link to the Digital software (GitHub). (Greg)
  • Release a lab due next week (target: Thursday night) requiring schematic entry, circuit construction, and simulation in Digital. (Greg)
  • Continue from the SR latch to a register and toward a 64-bit register in the next session (Tuesday). (Greg)

FPGA and Hardware Classroom Experience

  • Greg discussed classroom experience with hardware and electronics, including Raspberry Pi and FPGA-based projects.
  • He contrasted FPGAs with ASICs and noted an interest in further exploring FPGAs, particularly for AI-related work.
  • He reiterated plans to take live notes during meetings and later publish formal notes on the website.

Combinational Logic Design Overview

  • The difference between combinational and sequential logic was clarified:
  • Combinational logic has no state; outputs depend only on current inputs.
  • Sequential logic maintains state over time.
  • The course roadmap moves from low-level digital design toward higher-level computing concepts (e.g., RISC-V assembly and machine code).
  • Two approaches to digital design were outlined:
  • Schematic entry (virtual circuits in software)
  • Physical design (real components and wiring)

New Hardware Description Language Development

  • Greg is developing a new HDL targeted for an initial release next week.
  • Motivation: while Verilog and VHDL are industry standards, they can be complex with steep learning curves.
  • Goals:
  • Provide a more natural mapping from circuit design to code.
  • Enable the “pod” to better understand and reason about circuits.
  • He emphasized the progression from high-level software down through layers to low-level hardware.

Digital Logic Fundamentals

  • Analog voltages are disciplined into binary values via thresholds, yielding logical 0s and 1s.
  • Basic components introduced:
  • Wires and power sources
  • Logic gates: AND, OR, NOT
  • Boolean algebra uses variables constrained to {0, 1} and operators corresponding to gate behavior.

Propositional Logic and Boolean Algebra

  • Symbols and operators for AND, OR, and NOT were mapped to truth tables and circuit symbols.
  • The relationship between Boolean expressions and circuit diagrams was demonstrated.
  • An example combinational circuit was used to show how values propagate through gates.

8-Bit Adder Design

  • Objective: build an 8-bit adder using buses (collections of wires carrying multi-bit values).
  • The Sum of Products (SoP) technique allows defining functions from truth tables and building circuits accordingly.
  • Greg noted confidence in scaling these methods up to a 64-bit processor based on extensive experience.

Boolean Equations from Truth Tables

  • The SoP technique was demonstrated:
  • Enumerate input combinations (powers of 2 with alternating 0/1 patterns).
  • Select rows where the output is 1.
  • Form product terms (ANDs of literals) and sum them (OR) into a Boolean equation.
  • For a simple one-bit sum, an XOR gate is more efficient than an SoP with three gates.

Circuit Representation for Sum of Products

  • Implementation pattern:
  • Use AND gates to realize each product term.
  • Use an OR gate to combine them into the final output.
  • Standard notation was reviewed:
  • Dots indicate wire junctions.
  • Bubbles indicate inversion (NOT).
  • The Digital software tool was used to:
  • Create inputs/outputs
  • Draw and connect wires
  • Place and configure gates

Electric Circuit Simulation

  • A simulation showcased signal flow through a 1-bit adder, with colors indicating logical values.
  • Key idea: build complex computations by composing smaller functional blocks.
  • The path toward an 8-bit adder via multiple 1-bit adders was outlined, with a full-adder demonstration planned.

One-Bit Full Adder

  • A full adder has three inputs (A, B, Carry-In) and two outputs (Sum, Carry-Out).
  • An 8-row truth table defines behavior.
  • The Sum output was derived via SoP and mapped to a circuit using multi-input AND/OR gates.

Digital Circuit Design Concepts

  • Abstraction and reuse enable modular design:
  • Example: a 4-bit ripple-carry adder created by chaining 1-bit full adders.
  • Carry ripple behavior:
  • Each adder’s Carry-Out feeds the next adder’s Carry-In.
  • Buses and splitters were introduced to group and extract individual bit values.

4-Bit Adder and Register Design

  • A 4-bit adder extends the 1-bit adder with 4-bit inputs A and B and a 4-bit Sum S; Carry-In and Carry-Out remain single-bit.
  • Adders are fundamental for operations such as PC increment and the add instruction.
  • Next objective: build a register (state-holding element) using latches, starting with the SR latch.

SR Latch and RAM Concepts

  • The SR latch built from cross-coupled NOR gates introduces feedback, making the circuit sequential.
  • RAM types:
  • Static RAM (SRAM): retains values while powered, no refresh required; typically faster, less dense.
  • Dynamic RAM (DRAM): uses capacitors; higher density and lower cost but requires refresh.
  • Planned progression:
  • SR latch → register (e.g., 64-bit) → processor components.
  • Upcoming lab (due next week): schematic entry and circuit simulation in Digital.