Meeting Summary: CS 631-01 Systems Foundations¶

Quick Recap¶

Greg taught a digital design session on processor implementation, focusing on the fundamentals of a single-cycle CPU.
Key components covered: program counter (PC), instruction memory (ROM), register file, and ALU.
The class built a 4-bit counter, then discussed how counters, registers, and the ALU integrate within a processor architecture.
Differences between single-cycle and multi-cycle processors were emphasized, along with an overview of modern techniques such as pipelining and speculative execution.
The session concluded with plans to complete the register file and cover the ALU and instruction decoding in the next class on Tuesday.

The lab assignment was delayed to next week.
The session built on combinational and sequential logic concepts to construct a 4-bit counter using:
A register to hold the current count
An adder to compute the next count
Control signals: clock, enable, and clear
Clarification: the register outputs the current count, not the next value.
Students were encouraged to ask questions about the circuit design.

The design and behavior of a 4-bit register were reviewed, focusing on:
D flip-flops with enable and clear functionality
The behavior of D latches and SR latches
A one-bit adder was introduced, leading to the concept of a 4-bit ripple-carry adder.

A 4-bit ripple-carry adder was demonstrated in a digital design tool, including:
Customizing labels and layout
Aligning inputs/outputs and managing visual settings
Copying components to speed up design
Using splitters to break a 4-bit bus into individual bits (syntax details to be finalized)

A digital counter circuit was used to illustrate rising/falling edge behavior.
The discussion generalized to a processor model:
Core elements: state registers, combinational logic, and a clock
Representative state: general-purpose registers (X0–X31), PC, and data memory
Example instruction behaviors: arithmetic (e.g., addition), branching, and memory access

A high-level processor diagram was refined into concrete components:
Instruction memory implemented as ROM with 32-bit instruction words
Use of library components rather than building every primitive from scratch
An instruction decoder to process fields from instruction words, echoing prior emulator work

Architecture highlights:
Key blocks: register file, ALU, memory access
Each instruction completes in one clock cycle
Clock period is constrained by the longest combinational path
Historical context:
Multi-cycle designs were common in the 1970s
Modern CPUs use parallelism techniques such as pipelining and speculative execution

Upcoming topics: program counter, instruction memory, register file, ALU, and decoding.
Scheduling/details:
Two course sections are running
A student (Anderson) may assist as a TA for one session
Tooling plans:
Instruction in Rust
Containerized environments (Docker Desktop with WSL integration on Windows)

Program counter:
A 64-bit register with clear functionality was configured using a digital register component
Instruction memory (ROM):
Configured for 32-bit instruction words
8-bit address input, supporting 256 instructions
Addressing:
A splitter converts the 64-bit byte address to a word address by extracting the relevant bits

A simple RISC-V program was implemented using a spreadsheet-like workflow:
Instruction words were populated into ROM
A PC register and adder advanced through instructions
The next planned topic was the register file (discussion to continue next session).