CS 631-01 Systems Foundations — Meeting Summary¶

Quick Recap¶

In this digital design lecture, Greg continued the fundamentals of implementing a computer processor at the digital logic level. He:

Traced the progression from combinational logic to sequential logic by building a 4-bit counter using a 4-bit ripple-carry adder and a 4-bit register.
Reviewed the SR latch, its evolution into a D latch, and finally a D flip-flop with clear and enable controls.
Demonstrated circuit construction using digital logic tools, emphasizing the role of clock signals—particularly the rising edge—in controlling state changes.
Concluded with instructions for a lab where students implement a 4-bit counter based on the lecture’s concepts.

Greg: Release the lab assignment on schematically building circuits with the digital tool later today.
Students: Complete the lab (implement a 4-bit counter using a 4-bit adder and 4-bit register in the Digital tool) and submit it as this week’s lab.
Greg: Open the next class (Thursday) with a live demonstration of building a 4-bit counter by combining a 4-bit adder, 4-bit register, and a clock.

Greg set the agenda to build a shortest path to understanding processor implementation at the digital logic level.
This week’s lab focuses on schematic circuit design in a digital tool and should take about 1–2 hours.
The class will transition to processor design on Thursday after covering core concepts, including:
Implementing a 4-bit counter using a 4-bit ripple-carry adder, a 4-bit register, and a clock.

The SR latch was reviewed as a foundation for building registers.
SR latches act as a form of static RAM (retaining state as long as power is applied), in contrast to dynamic RAM.
Behavior with initial conditions and inputs was demonstrated, highlighting how the latch maintains a stored value.

Greg showed how different input combinations propagate through the latch and how the output is retained.
He emphasized the single undefined state when both S and R are set to 1 simultaneously and why designs must avoid this.
He introduced the clock signal concept (oscillating between 0 and 1), noting that computers use crystal-based oscillators.

The lecture outlined rising and falling edges of the clock and how edges define controlled state changes.
Limitations of the SR latch led to the D latch, which uses the clock and a single data input D to control updates.
An implementation approach using AND gates was proposed to gate inputs based on the clock.

By constraining inputs, the formulation ensures that either both R and S are 0 or exactly one is 1 at any time.
A live simulation (with labeled R, S, and Q) demonstrated behavior from Q = 0 transitioning to Q = 1 across runs.

Greg built an SR-based circuit using D and clock inputs to show how values are latched when the clock is high.
He demonstrated saving the circuit as a custom component for reuse and introduced a data graph view to visualize signals over time.
The class then prepared to cover multiplexers before a short break.

A multiplexer (MUX) was introduced as a data selector that routes one of multiple inputs to the output using a selector signal.
Implementation used AND gates feeding an OR gate, with the selector choosing between inputs (e.g., A vs. B).
Greg showed how different input combinations affect the output and stressed that MUXes are core building blocks in digital systems and processors.

Larger MUXes can be composed from smaller ones; a 4-input MUX example used a 2-bit selector.
Bit-width scaling was demonstrated by splitting each bit into separate gated paths.
After this, the class took a 10-minute break before moving on to build a D flip-flop and a 1-bit register, leading toward a counter.

A D flip-flop updates its output at a specific time: the clock’s rising edge.
Construction uses two cascaded D latches: the first preloads the data; the second commits it on the 0→1 transition.
Note: In digital logic tools, all inputs must be connected, while outputs may remain unconnected. Symbols can be resized for clarity.

Greg showed how to extend a D flip-flop into a register with enable and clear:
Use a multiplexer to select between the current value (hold) and the new data (write) based on the enable signal.
Implement a synchronous clear by routing a hardwired zero through another multiplexer.
The session wrapped with plans to construct a 4-bit register and explore building a 4-bit counter or adder on Thursday—the focus of the upcoming lab.