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Meeting Summary: CS 631-01 Systems Foundations

  • Date: Apr 21, 2026
  • Time: 08:16 AM Pacific (US and Canada)
  • Meeting ID: 870 0988 0761

Quick Recap

Professor Greg led a session on: - Project 4: Populating control lines in a spreadsheet to generate a decode ROM .hex file for a RISC-V processor project. - Advanced computer architecture: pipelining, superscalar and out-of-order execution, branch prediction, caching, and multi-core design. - Transition to operating systems: introduction to Octoks, a Rust implementation of the XV6 teaching OS (Unix-style, RISC-V), to teach core OS concepts.

Next Steps and Collaboration

  • All students: Complete Project 4 by populating the spreadsheet with control lines and generating the correct decode ROM .hex file. Submit by next Monday.
  • All students: Set up the autograder (Rust or C version) on macOS or another appropriate environment.
  • Ensure the Digital tool is in the expected directory.
  • Update config.tamel if necessary to set the Digital path.
  • All students: Clone the Octoks repository, follow the guide, and get Octoks running in preparation for the OS unit.
  • All students: Begin reading the Octoks guide and walkthroughs as assigned.

Detailed Summary

Project 4: Spreadsheet Control Lines

  • Focus: Populate a spreadsheet that drives the decode ROM by setting control lines per instruction.
  • Spreadsheet structure includes:
  • Instruction names and format types.
  • Fields/inputs needed for instruction identification.
  • Decoder logic mapping to control-line outputs for each instruction.
  • Emphasis on correctness of control outputs for all instruction variants.

Converting Spreadsheet Output to .hex

  • Task: Extract output bits from the spreadsheet and convert them into a .hex file for the decode ROM.
  • Key requirements:
  • The first line of the file must be: “V2.0 space raw”.
  • Conversion can be done via manual copy or spreadsheet formulas/macros.
  • Clarifications:
  • Function 6 handling and encodings for SLLI, SRLI, and SRAI were reviewed.
  • Running tests:
  • Run from the top-level project directory.
  • Either place Digital in the expected home-directory path or set the path in config.tamel.
  • The Rust autograder version is often easier to set up on macOS.

Rust Autograder Setup (macOS)

  • Addressed macOS security and quarantine issues:
  • Move files as needed and bypass Gatekeeper prompts where appropriate.
  • Ensure tests are executed in the repository’s top-level directory.
  • Noted a minor UI initialization issue on some Macs that can temporarily affect terminal focus during test runs.

Processor Design Advancements

  • Two major dimensions:
  • Physical process scaling: Smaller transistors (e.g., 7 nm → 3 nm) enable more gates per chip, larger caches, and richer microarchitecture. Speed may improve slightly due to shorter distances, but the primary gain is greater on-chip complexity.
  • Microarchitecture: Organizing gates for more sophisticated execution engines, evolving from early ICs to modern multi-chip and multi-core processors.

Computer Architecture Evolution and Performance

  • Historical arc:
  • From early personal computers/hobbyist scenes to modern CPUs.
  • Market successes (e.g., Apple) stemmed from combining the right features with strong execution—paralleling later tech companies.
  • Performance focus shifted:
  • From raw clock-rate increases to improving instructions per cycle (IPC).
  • Pipelining divides instruction processing into stages to boost throughput.

Pipelining: Hazards and Example

  • Pipelining improves throughput but introduces hazards:
  • Data dependencies, control hazards, and structural conflicts.
  • Mitigations include cache hierarchy design and increasingly sophisticated branch prediction (sometimes ML-assisted).
  • Example discussed:
  • A linked list traversal and count in assembly used in a project test case, illustrating how dependencies and control flow interact with pipeline behavior.

Superscalar, Out-of-Order, and Caching

  • Superscalar execution runs multiple instructions per cycle when dependencies allow.
  • Out-of-order execution with register renaming lets processors bypass false dependencies and keep functional units busy.
  • Instruction execution times vary significantly; caching is critical to performance.
  • Deep pipelines raise the cost of mispredicted branches; accurate prediction is essential.

Branch Prediction and Multi-Core Processing

  • Branch prediction evolved from simple heuristics to ~97% accuracy in modern CPUs.
  • Clock speed scaling hit limits due to power and thermal constraints.
  • Multi-core architectures provide performance via true concurrency rather than higher single-core frequency.

Octoks: Teaching Operating System (Rust, RISC-V)

  • Octoks is a Rust implementation of the XV6 teaching OS for RISC-V.
  • Context:
  • XV6 is a Unix-like teaching OS from MIT, originally in C for x86, later ported to RISC-V.
  • Course plan:
  • Students will explore process scheduling, process creation, console I/O, and other OS fundamentals.
  • A dedicated guide and walkthroughs are available; students should set up Octoks before the next class (Thursday).