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CS 631-01 Systems Foundations — Meeting Summary

Date: April 14, 2026
Time: 08:16 AM Pacific (US & Canada)
Meeting ID: 870 0988 0761

Quick Recap

  • Greg led a discussion on software flaws and trusted systems, concluding that humans alone may not be able to build complex, trusted software without significant support from tools and safer languages (e.g., Rust).
  • He demonstrated GGL (Golden Gate Language), a new language for specifying circuits that can automatically generate both circuit descriptions and visual schematics using the Elk diagramming library.
  • The session covered processor components, including the register file, ALU, and instruction memory, and showed how these parts can be connected and tested via a visual interface.
  • The group agreed to continue the processor implementation, adding decoding logic to interpret instruction words and control processor operations.

Next Steps

  • Greg: Add a synchronous clear input to register components in GGL.
  • Greg: Complete tunnels and virtual connections in GGL schematic mode and resolve current issues.
  • Greg: Add dynamic value display/interactivity in GGL schematic mode.
  • Greg: Finish instruction decoding logic for the processor’s digital logic components (Thursday).
  • Greg: Provide students with a partial GGL processor implementation as a starter (with gaps such as decoder, ALU, etc.).
  • Greg: Develop and deliver auto-graded tests for GGL circuits (similar to CS 315).

Detailed Summary

Trusted Software Development Challenges

  • Greg reviewed high-profile flaws in systems such as Linux, Windows, and web browsers.
  • Key position: fully trusted, flaw-free complex software is likely unattainable without assistance from safer languages and tools.
  • Rust and similar approaches can reduce classes of errors to an acceptable tolerance level.
  • Human fallibility and varying diligence in software development were noted as major risk factors.

Programmatic Circuit Design with GGL

  • GGL (Golden Gate Language) enables programmatic specification and execution of circuits.
  • Features:
  • Human-readable syntax and LLM-friendly structure.
  • Automatic schematic generation via Eclipse’s Elk diagramming library.
  • Layout influence through virtual grids without requiring explicit wiring for every connection.
  • Demonstrations covered simple gates (AND) and more complex designs (8-bit register).

Python-Driven Circuit Design

  • Greg showed Python-based construction of circuits, including an 8-bit counter using list comprehensions and GGL syntax.
  • Workflow:
  • GGL specifies circuits and can simulate them directly.
  • Schematic generation involves producing HTML with embedded JSON processed by Elk JS to render readable diagrams.

Digital Instruction Memory System

  • A working instruction memory was demonstrated:
  • 32-bit instruction words stored in ROM.
  • A splitter retrieves instructions based on the program counter (PC).
  • Vision:
  • Author circuits directly in GGL.
  • Potential future path to FPGA-based implementations.
  • Core processing model: combinational logic + stateful registers + clocks driving instruction execution and register control.

Single-Cycle Processor Implementation

  • Components discussed: PC, 64-bit registers, instruction memory (ROM for initial programs), and the register file.
  • Initial approach uses fixed programs via ROM for simplicity; RAM will be introduced later for the stack.
  • Upcoming addition: synchronous clear input for GGL’s digital register component.

Processor Components Overview

  • Register File:
  • Supports simultaneous read/write through MUXes and decoders for selection and enable control.
  • ALU:
  • Built from existing components (adder, subtractor, multiplier, shifters).
  • Operation selected via a control signal.
  • Pedagogy:
  • Balance between providing a full reference design and leaving meaningful gaps for student learning.

ALU Implementation Planning

  • Plan to compose ALU functionality from proven subcomponents with a selector for operations.
  • Emphasis on thorough test coverage using auto-graded GGL circuit tests, aiming to exceed current CS 315 coverage.

Development Approach

  • Strategy: incremental development and testing.
  • Use of coding agents (e.g., Cloud Code) to plan staged implementation.
  • Current/proposed elements:
  • PC, digital registers with synchronous clear, register file.
  • Instruction memory via ROM (supporting multiple programs), selected via a MUX.
  • Simple instruction programs for stepwise validation.

Processor Design and Visualization

  • Instruction memory, PC, adder, register file, and ALU integration was outlined.
  • Data routing relies on multiplexers for selecting destinations.
  • Need identified: surfacing register values during simulation for easier debugging.
  • ALU includes add, subtract, multiply, and shift operations; visualization and simulation remain key challenges.

ALU Multiplication Details

  • Multiplication uses 32-bit inputs, producing a 64-bit result; operations were shown with manual register value setup.
  • Next milestone: implement instruction decoding to automatically set control lines and select ALU operations based on the instruction word.
  • Target: continue on Thursday with the goal of enabling participants to understand and implement a complete processor.