Digital Design 2: Sequential Logic

# Digital Design 2

## Sequential Logic

### CS 631 Systems Foundations — Apr 7, 2026

---

## Today's Agenda

1. Combinational → sequential; SR latch; SRAM vs DRAM
2. Clock signals; D latch
3. Multiplexers (2:1, 4:1)
4. D flip-flop (master–slave)
5. 1-bit register with EN MUX + CLR MUX
6. N-bit register → 4-bit counter

---

## Why We Need State

Combinational circuits have **no memory** — outputs depend only on current inputs.

A processor obviously does have memory:

- Register file, program counter
- Condition flags
- RAM

**Today's goal**: build an N-bit register and a counter.

---

## Combinational vs Sequential

| Property | Combinational | Sequential |
|----------|---------------|------------|
| Output depends on | Inputs only | Inputs **and** state |
| Memory | None | Has storage |
| Clock | Not required | Required |
| Feedback | No | Yes |
| Examples | Adders, MUXes | Latches, registers |

<div class="info-box">
<strong>Feedback</strong> is the mechanism that adds state.
</div>

---

## SR Latch — Cross-Coupled NORs

```
  R ───┬── NOR ───┬── Q
       │          │
       │    ┌─────┘  (feedback)
       │    │
       │    └──────┐
       │           │
  S ───┴── NOR ───┴── Q̄
       │           │
       └───────────┘  (feedback)
```

- **S = 1** → set Q to 1
- **R = 1** → reset Q to 0
- **S = R = 0** → hold last value (state!)

---

## SR Latch Truth Table

| R | S | Q | Q̄ | State |
|---|---|---|---|-------|
| 0 | 0 | Q | Q̄ | Hold |
| 0 | 1 | 1 | 0 | Set |
| 1 | 0 | 0 | 1 | Reset |
| 1 | 1 | X | X | **Forbidden** |

<div class="highlight-box">
S = R = 1 forces Q = Q̄ = 0. Final state is undefined when both return to 0 — avoid this combination.
</div>

---

## SRAM vs DRAM

| | SRAM | DRAM |
|---|------|------|
| Stores bit as | Cross-coupled latch (~6 T) | Capacitor charge (1T + 1C) |
| Speed | Fast | Slower |
| Density | Low | High |
| Refresh | Never | Periodic |
| Used for | Caches, registers | Main memory |

The SR latch is the heart of every SRAM cell.

---

## Clock Signals

```
        ┌───┐   ┌───┐   ┌───┐
    1 ──┘   └───┘   └───┘   └───
        ↑   ↓
     rising  falling
      edge   edge
```

| Term | Meaning |
|------|---------|
| Rising edge | 0 → 1 transition |
| Falling edge | 1 → 0 transition |
| Period | Time for one full cycle |
| Frequency | Cycles per second (Hz) |

Real hardware: **crystal oscillator**.

---

## Level- vs Edge-Triggered

- **Level-triggered (latch)**: can change while clock is at a level.
- **Edge-triggered (flip-flop)**: changes only at a clock edge.

<div class="info-box">
Modern processors use <strong>edge-triggered</strong> storage for predictable timing.
</div>

---

## D Latch

Gate D and its complement by the clock, feed into an SR latch:

<div class="mermaid">
flowchart LR
    D[D] --> AND1[AND]
    D --> NOT[NOT]
    NOT --> AND2[AND]
    C[C] --> AND1
    C --> AND2
    AND1 --> |S| SR[SR Latch]
    AND2 --> |R| SR
    SR --> Q[Q]
</div>

S = D · C, R = D̄ · C → S and R never both 1.

---

## D Latch Behavior

| C | D | Q |
|---|---|---|
| 0 | X | No change |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

- While **C = 1**, Q follows D (transparent).
- When **C = 0**, Q holds its last value.

<div class="highlight-box">
Built live in the Digital simulator — saved as a custom component, verified with the data-graph view.
</div>

---

## Multiplexer (2:1)

A **MUX** selects one of several inputs based on a select signal.

```
         s
         │
     a ──┤0│
         │ ├── r
     b ──┤1│
         │
```

- If s = 0 → r = a
- If s = 1 → r = b

**Boolean**: r = (a · s̄) + (b · s)

---

## 2:1 MUX — Gate Level

<div class="mermaid">
flowchart LR
    S[s] --> NOT[NOT]
    NOT --> AND1[AND]
    A[a] --> AND1
    S --> AND2[AND]
    B[b] --> AND2
    AND1 --> OR[OR]
    AND2 --> OR
    OR --> R[r]
</div>

Direct SoP: one NOT, two ANDs, one OR.

---

## 4:1 MUX from Three 2:1 MUXes

| s₁ | s₀ | r |
|----|----|----|
| 0 | 0 | a |
| 0 | 1 | b |
| 1 | 0 | c |
| 1 | 1 | d |

</div>
<div>

<div class="mermaid">
flowchart LR
    A[a] --> M1[2:1]
    B[b] --> M1
    C[c] --> M2[2:1]
    D[d] --> M2
    S0[s₀] --> M1
    S0 --> M2
    M1 --> M3[2:1]
    M2 --> M3
    S1[s₁] --> M3
    M3 --> R[r]
</div>

</div>
</div>

---

## Why the D Latch Isn't Enough

While C = 1, a D latch is **transparent**: any change on D immediately updates Q.

With feedback (register output → input) this races through multiple updates in one cycle.

<div class="highlight-box">
We want <strong>exactly one update per clock cycle</strong>, at a well-defined moment.
</div>

---

## D Flip-Flop — Master–Slave

<div class="mermaid">
flowchart LR
    D[D] --> M[D Latch<br/>Master]
    CLK[CLK] --> NOT[NOT]
    NOT --> M
    M --> S[D Latch<br/>Slave]
    CLK --> S
    S --> Q[Q]
</div>

- CLK = 0: master transparent, slave locked
- CLK = 1: master locked, slave transparent
- **Rising edge**: master freezes D, slave publishes it

Q updates **only** on the rising edge.

---

## D Flip-Flop Timing

```
CLK:  ____┌────┐____┌────┐____┌────┐____
          │    │    │    │    │    │
D:   ──XX─┤XXXX├────┤XXXX├─XXX┤XXXX├────
          │    │    │    │    │    │
Q:   ─────┤    ├────┤    ├────┤    ├────
          ↑         ↑         ↑
       captures  captures  captures
```

Between edges Q is stable even if D changes.

---

## 1-Bit Register: DFF + Two MUXes

<div class="mermaid">
flowchart LR
    D[D] --> EM[EN MUX] --> CM[CLR MUX] --> FF[D FF] --> Q[Q]
    Q -.->|feedback| EM
    EN[EN] --> EM
    ZERO[0] --> CM
    CLR[CLR] --> CM
    CLK[CLK] --> FF
</div>

EN MUX: hold (Q) vs. load (D). CLR MUX: pass vs. 0. All changes **synchronous** (next rising edge).

---

## Register Control Table

| CLR | EN | Next Q |
|-----|-----|--------|
| 1 | X | 0 (clear) |
| 0 | 0 | Q (hold) |
| 0 | 1 | D (load) |

<div class="info-box">
CLR sits <strong>after</strong> the EN MUX — it overrides EN when both are 1.
</div>

---

## N-Bit Register

N D flip-flops in parallel — each with its own EN MUX + CLR MUX — sharing **CLK**, **EN**, **CLR**.

```
    D[N-1:0]
       │
   ┌───▼───────────────────────┐
   │ FF  FF  FF  FF  ...  FF   │
   │                           │
   │ Q[N-1:0]                  │
   └───┬──┬───┬────────────────┘
      CLK EN CLR  (shared)
```

A **4-bit register** is the building block for a 4-bit counter.

---

## 4-Bit Counter

<div class="mermaid">
flowchart LR
    REG[4-bit Register] --> ADD[4-bit Adder]
    ONE[1] --> ADD
    ADD --> REG
    CLK[CLK] --> REG
    CLR[CLR] --> REG
    REG --> OUT[count]
</div>

- Each rising edge: new = current + 1
- CLR resets count to 0
- Wraps at 15 → 0 (overflow)

---

## Key Takeaways

- **Feedback** turns combinational into sequential.
- **SR latch** → D latch → D flip-flop (master–slave).
- **Edge-triggered** storage = predictable timing.
- **MUX** = data selector; two MUXes give us sync EN + CLR.
- **Register + adder + 1** = counter.