Project04 - RISC-V Processor Decoder¶
Due Mon Apr 27nd by 11:59pm in your Project04 GitHub repo
Links¶
Tests: https://github.com/USF-CS631-S26/tests
Background¶
The goal of this project is to learn a specific micro architecture for the RISC-V instruction set architecture. Your goal will be to complete the decoder portion of the implemenation so that the processor can execute the same RISC-V programs that your RISC-V emulator could execute.
See the Project04 tests and given code for details.
Details¶
You are given a complete top-level data and control path with components for a RISC-V single cycle processor. What is missing is the complete Decode ROM content that will make the processor work for each instruction. You are given a Decoder spreadsheet that you can use to construct the control line values. Your goal is to derive the control line values for each instruction so that eventually all the tests pass.
To generate a .hex file to load into the Decode ROM you need to copy the Output bits - binary column context to a file, call it output_bits_bin.txt.
Then use the given mkdecoderom.py Python program to convert this file in to a proper .hex file that is understood by Digital:
Alternatively, you can copy the Output bits - hex column directly to output_bits.hex and add the follow line at the top of this file:
I recommend that you work on the instructions incrementally.
Grading¶
Grading is based on automated tests (100 points total).