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CS 631-02 Systems Foundations — Meeting Summary

  • Date: May 07, 2026
  • Time: 02:51 PM Pacific Time (US and Canada)
  • Meeting ID: 882 2309 0019

Quick Recap

The lecture covered two major areas: - Process scheduling on a single core, including user/kernel mode transitions, timer interrupts, and context switching. - Virtual memory and page tables, focusing on virtual-to-physical address translation and why multi-level page tables are necessary.

Key Topics and Details

Process Scheduling and Time Slicing

  • A mental model was introduced using a 100 ms time slice to illustrate how multiple processes share a single CPU.
  • Timer interrupts periodically transfer control to the kernel, which decides which process runs next.
  • Modern kernels (e.g., Linux) adjust timing and scheduling decisions dynamically based on workload.
  • Choosing time-slice length involves trade-offs: long enough to do useful work but short enough to maintain responsiveness and fairness.

OS Mode Transitions and Traps

  • Transitions from user to kernel mode occur via:
  • System calls (voluntary)
  • Timer/device interrupts (involuntary)
  • Faults and exceptions (e.g., invalid memory access), which can terminate the process
  • The kernel handles these events through trap handlers, then either resumes the same process or schedules another.

Context Switching Mechanics

  • Context switching saves the current process’s state and restores another’s.
  • The discussed switch routine (RISC-V) saves and restores callee-saved registers, relying on calling conventions that already preserve caller-saved registers.
  • Switching may involve returning to a user process after an interrupt, or jumping into the scheduler context to select a different process.

Kernel Scheduler Architecture

  • Each CPU runs an infinite scheduling loop:
  • Scan for a runnable process.
  • Switch to it.
  • On the next trap/interrupt, repeat.
  • Transitioning to a per-CPU scheduler context enables the kernel to choose the next process safely.

Rust in OS Kernels

  • Writing a kernel requires operations (e.g., direct memory management, page table manipulation) that inherently need unsafe code.
  • Conclusion: a fully safe-Rust kernel is not feasible; some unsafe blocks are necessary to implement core OS responsibilities.

System Initialization (Octux and Maine)

  • Octux:
  • Kernel initialization sets up CPU, memory, and the process table.
  • The init.rs process configures the first three file descriptors and launches the shell.
  • GUI applications typically interact with the kernel via direct system calls, not by invoking shell commands.
  • Maine:
  • CPU0 performs early initialization; additional CPUs start after CPU0 completes.
  • Initially, only the init process is runnable; all cores then enter the scheduling loop.

Memory Architecture and Kernel Mapping

  • Kernel virtual memory is mapped above the 2 GB boundary; user processes use memory below it.
  • System calls transition to kernel mode via trampoline code to safely enter kernel functions.
  • User memory is allocated from free RAM remaining after kernel code/data are loaded.
  • Future sessions will detail page table data structures.

Virtual Memory and Page Tables (32-bit example)

  • With 32-bit addressing and 4 KB pages:
  • Address space: 4 GB
  • Page size: 4 KB
  • Total pages: ~1,048,576
  • Address breakdown:
    • Page number: upper 20 bits
    • Page offset: lower 12 bits
  • Virtual memory maps virtual pages to physical page frames, allowing processes to use more virtual address space than physical RAM.

Virtual Address Translation and Multi-Level Page Tables

  • Single-level page tables become too large to allocate entirely for each process.
  • Multi-level page tables (e.g., L1 → L0) allocate page table memory only for mapped regions, dramatically reducing memory overhead.
  • Next steps (planned): TLB (Translation Lookaside Buffer) behavior and virtual memory implementation on RISC-V 64-bit.

Next Steps

  • No formal next steps were generated due to an incomplete transcript.
  • Anticipated topics: TLBs, RISC-V Sv39/Sv48 page table formats, and detailed page table data structures.

Key Takeaways

  • Time-sliced scheduling with timer interrupts enables fairness and responsiveness on a single core.
  • Context switches rely on calling conventions; only callee-saved registers need saving in the switch routine.
  • Multi-level page tables solve scalability issues inherent to single-level designs.
  • OS kernels require controlled use of unsafe operations; fully safe implementations are not practical.