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Meeting Summary: CS 631-02 Systems Foundations

Apr 14, 2026 — 02:50 PM Pacific Time (US and Canada)
Meeting ID: 882 2309 0019

Quick Recap

In this computer architecture lecture, Greg continued demonstrating the development of a RISC-V processor using a Python-based circuit specification language called GGL (Golden Gates Language). He explained the implementation of key components—including the register file, ALU, and instruction memory—and showed how these elements work together to execute simple programs. The lecture covered data paths versus control paths in digital design and emphasized incremental development for building complex circuits. Greg discussed the evolution of processor design from basic components to broader instruction support and outlined plans to provide students with a partial processor implementation to extend as a lab, before transitioning to the next segment on operating systems.

Next Steps

  • Greg: Complete the GGL implementation of the ALU and other processor components.
  • Greg: Prepare and distribute a partial GGL processor implementation for students to extend as a lab assignment.
  • Greg: Convert all lecture content, including iPad notes, into full written lecture notes.
  • Greg: Provide the new lab assignment to students.

AI Tools and Circuit Schematics

  • Greg shared observations on AI tools and their addictive nature, likening them to Tamagotchi devices.
  • He emphasized the importance of visual circuit schematics for reasoning about hardware:
  • Unlike sequential code, circuits operate concurrently.
  • Visual representations aid understanding of signal propagation and digital logic.
  • He noted that while schematic work can feel repetitive, it remains valuable for learning and design clarity.

Python Circuit Design Demonstration

  • Greg demonstrated a Python-based approach to programmatically specify and generate digital circuits, starting with an AND gate.
  • He outlined a vision for using LLMs to collaboratively assist in circuit design, enabling more intuitive and automated workflows.
  • He showed how code-generated specifications can be converted automatically into schematics and previewed plans to explore more complex examples (e.g., a full adder).

Digital Circuit Design Tool Demo

  • Greg showcased a new tool for programmatic circuit diagram generation and simulation.
  • Capabilities demonstrated:
  • Construction of ripple-carry adders, register files, and other components.
  • Trade-offs between building from primitives versus using pre-built components.
  • He noted that while the tool supports basic simulation, heavy reliance on emulated gates can slow simulations compared to native component abstractions.

Processor Design Progress Review

  • Reviewed combinational and sequential logic progress:
  • Built a 4-bit adder and a 4-bit register.
  • Explained processor basics:
  • Program counter (PC) behavior and instruction execution flow.
  • Shared timeline:
  • Targeting completion of the register file, ALU, and possibly RAM by Thursday.
  • Goal: a processor capable of interpreting and executing RISC-V instructions at the digital logic level.

Processor Register Write Mechanism

  • Instruction fields:
  • RD bits select the target register.
  • WD (64-bit write data) provides the value to store.
  • A decoder will map the 5-bit register number to a one-hot signal to update exactly one of 32 registers.
  • Introduced “tunnels” (virtual connections) to carry shared signals (e.g., clock and clear) without explicit wires for clarity in schematics.

Register File Write Enable Design

  • Strategy for write enable (WE):
  • Use a MUX to pass the write register value when WE = 1; force 0 when WE = 0 so writes are ignored.
  • Noted that multiple register outputs are exposed in simulation for debugging, while a real RISC-V-style design would typically expose only functional outputs (e.g., RD0, RD1).

Multiplexer Design and Circuit Analysis

  • Explained multiplexers (MUXes) with analogies (home theater receiver, KVM switch).
  • A 32-input MUX selects one of 32 registers using 5 selector bits.
  • Discussed decoder complexity for deriving ALU operations from instruction words.
  • ALU design approach:
  • Use MUXes to select among candidate arithmetic/logic results based on decoder output.
  • Emphasized a hardware mindset:
  • All gates compute continuously; unlike software, they cannot be “disabled” selectively.

Computational Architecture and ALU Demonstration

  • Described a compute-everything approach (speculative-like), which can appear wasteful but supports high performance.
  • Mentioned practical challenges of low-level power management (e.g., disabling components vs. clock gating), citing Transmeta as context.
  • Demonstrated an incomplete but working ALU:
  • Showed addition, subtraction, and multiplication.
  • Discussed bit-width handling and result truncation for multiply operations.

Hexadecimal CPU System Implementation

  • Clarified the role of hexadecimal:
  • Hex is a compact representation of unsigned binary with a 1:1 mapping per nibble.
  • Like binary, hex has no inherent notion of negativity; negative values are represented via complements (e.g., two’s complement).

Development Environment and Project Updates

  • Shared tooling preferences:
  • Prefers terminal-based development over IDEs such as VS Code and IntelliJ.
  • Noted issues running Claude Code inside IntelliJ terminals; VS Code terminals were more reliable.
  • Project status:
  • ALU construction completed; current focus is connecting the register file.

Incremental Development in Complex Projects

  • Advocated for incremental, dependency-aware development in complex systems.
  • Drew parallels to teaching computer architecture and programming.
  • Highlighted Cloud Code’s “Tasks” feature for structuring work with dependency graphs.
  • Implementation approach for GGL:
  • Build incrementally, starting with a simple simulation panel before adding features.
  • Stressed the balance between plan-driven and adaptive iteration, noting that even graduate-level efforts benefit from staged construction.

Processor Circuit Building Demonstration

  • Walked through manual execution of simple add instructions on a constructed data path.
  • Highlighted the need to manage data flow and ensure correct signal routing.
  • Positioned this as a stepping stone:
  • From first principles to modern complexity.
  • Next iteration: introduce a controller to automate operation sequencing.

Automated Switching System Transition

  • Transitioned from manual control to instruction-driven control:
  • The instruction word now drives splitters for RS1, RS2, and immediates.
  • Circuit interface minimized to essential inputs: clock, enable, clear, and program number.
  • Expanded the data path:
  • Added a second ALU input sourced from the PC.
  • Purpose: support PC+4 for normal flow and enable jump/branch target calculation by adding immediate offsets to the PC.

Processor Architecture Learning Plans

  • Reviewed instruction flow through the ALU, register file, and MUXes.
  • Shared a personal learning path in computer architecture and processor construction.
  • Teaching plan:
  • Provide students with a partial processor to extend as practice rather than building everything from scratch.
  • Prepare full written lecture notes alongside existing materials.
  • Upcoming: transition to the operating systems segment after the lab.