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CS 631-02 Systems Foundations — Meeting Summary

Date: Apr 09, 2026, 02:58 PM Pacific Time (US and Canada)
Meeting ID: 882 2309 0019

Quick Recap

The session focused on digital design and processor implementation. Greg guided students through: - Fundamentals of combinational and sequential logic (logic gates, D flip-flops, registers). - Building a 4-bit counter using a 4-bit adder and register (with clock, enable, and clear). - Implementing core processor components: program counter (PC), instruction memory (ROM), and a register file. - Using a digital design tool to configure registers, construct adders, and create multiplexers for register selection. - Comparing single-cycle and multi-cycle processors, and surveying modern techniques (speculative execution, parallelism). - Designing a register file supporting two reads and one write per clock cycle.

The full processor build will continue in the next session.

Next Steps

  • [ ] Greg: Distribute the lab assignment (8-bit counter and register file components). Due: middle of next week.
  • [ ] Greg: Provide scripts to populate ROM with instruction words for simulations.
  • [ ] Greg: Release the processor project (with scaffolding/framework). Due: the week after next.
  • [ ] Greg: Continue coverage next class (Tuesday): front half of the register file and remaining components.

Detailed Summary

Digital Design Fundamentals

  • Coverage included combinational logic gates and sequential components (latches, D flip-flops).
  • A 4-bit counter was outlined using:
  • A 4-bit adder and a 4-bit register.
  • Sum fed back to the D input.
  • Clock, enable, and clear controls.
  • Key idea: processors combine clock-driven state changes (sequential logic) with combinational logic to compute next state.

4-Bit Register Design

  • Design used D flip-flops and multiplexers (MUXes) to support enable and clear.
  • Internals included two D latches per flip-flop and synchronized clearing.
  • Emphasis on avoiding clock gating to prevent instability; clearing is handled synchronously.

4-Bit Adder and Circuit Construction

  • Demonstrated building a 4-bit adder in a digital design tool.
  • Showed:
  • Creating and customizing component symbols (labels, width, background, orientation).
  • Using splitters/mergers to manage multi-bit signals.
  • Best practices: inputs must be connected; outputs may remain unconnected if unused.
  • Multiplexers and splitters were highlighted as “glue” components for clean wiring.

4-Bit Counter Implementation

  • A single top-level clock drives all sequential elements down to the latches.
  • The counter increments via an adder (+1), counting 0–15 and wrapping around.
  • Clarification: using 0 on a given adder input acts as a neutral operand in this context.

Processor Architecture and Logic

  • An adder can act as a subtractor by inverting the B input and setting carry-in = 1.
  • Basic processor structure:
  • State: registers, PC, data memory.
  • Combinational logic: processes inputs and produces next-state values.
  • Execution model:
  • Read state, compute (e.g., ALU operations), write back results, update PC to fetch next instruction.
  • Instruction memory (ROM) introduced; further detail scheduled for the next session.

CPU Architecture Design

  • Read-Only Memory (ROM) compared to early BIOS.
  • A decoder splits 32-bit instruction words into fields and generates control signals.
  • Planned components:
  • Register file with 32 registers.
  • ALU for arithmetic/logic.
  • Two register operands supported by typical instructions.
  • Separation of instruction memory (ROM) and data memory (RAM) for simplicity.
  • A dedicated adder advances the PC by 4 bytes.

Single-Cycle vs. Modern Processors

  • Single-cycle processor:
  • Executes one instruction per cycle via PC → ROM → decoder → register file → ALU → write-back.
  • Simple but limited by long combinational paths; uncommon in modern designs.
  • Modern CPUs:
  • Use multi-cycle execution, speculative execution, and parallel units to improve throughput and latency.

Pipelines and Branchless Programming

  • Pipeline processors split instruction execution into stages, increasing throughput while keeping per-instruction latency similar.
  • Electrical behavior: PC latched on rising edge; signals propagate within the cycle.
  • On branchless-design-only architectures:
  • Considered impractical due to instruction bloat.
  • Existing CPUs sufficiently support branchless programming techniques.

Operating Systems: macOS vs. Windows

  • Security concerns noted with Windows (e.g., ransomware incidents).
  • macOS praised for Unix-based robustness and strong UI/aesthetics.
  • Windows historically advantaged in cost, gaming, and business software; modern Macs seen as competitively priced.
  • Personal shift to macOS cited for better hardware compatibility and reduced driver maintenance vs. Linux.

Processor Design Project

  • Brief context on evolving OS and UI complexity.
  • Announced project: extend a processor using provided scaffolding/framework.
  • Reviewed a 64-bit register’s control lines (clock, enable, clear) and a MUX + D flip-flop implementation.
  • Instruction memory component construction forthcoming.

ROM Test Harness

  • Built a harness to validate ROM functionality:
  • ROM configured with 32-bit instruction elements and appropriate addressing.
  • Address conversion between bytes and words via splitters (e.g., deriving an 8-bit word address from a 64-bit PC while ignoring low bits).
  • Simulation showed ROM with 32-bit data width and 8-bit address width.

RISC-V Processor Implementation Demo

  • Constructed a circuit combining registers, splitters, and ROM.
  • Added a 64-bit adder with a constant +4 for PC increment, plus clock and enable.
  • Populated ROM with instruction words via manual hex entry (using 0x prefixes).
  • Discussed alternatives:
  • Load from ROM files or embed programs directly; plan is to pre-create ROMs per program.
  • PC-driven ROM fetches were demonstrated, setting up further development.

Register File Design

  • Outlined a register file supporting:
  • Two simultaneous reads.
  • One write per clock cycle.
  • MUX-based selection logic.
  • Discussion paused due to time; to continue next week alongside completing the processor.
  • Announced schedule:
  • Lab due middle of next week.
  • Processor project the following week.
  • Transition to operating systems for the remainder of the semester.