CS 631-02 Systems Foundations — Meeting Summary¶

Quick Recap¶

In this digital design session, Greg introduced sequential logic circuits, building on prior work with combinational logic. The class:

Implemented foundational storage elements: SR latch → D latch → D flip-flop (with clear and enable) to form a 1-bit register.
Discussed clock signals, rising edges, and why clock gating should be avoided.
Used the Digital design software to construct and simulate circuits.
Built a 4-bit register and counter using splitters, mergers, and virtual connections, emphasizing proper wiring techniques.

Greg:
Complete the 4-bit counter circuit in Digital at the start of Thursday’s class.
Distribute the lab assignment (1-bit full adder → 4-bit adder; SR latch → 4-bit register; 4-bit counter).
Begin processor design in Thursday’s class, leveraging the 4-bit counter work.
Students:
Before Thursday, implement the sequence: 1-bit full adder → 4-bit adder → SR latch → 4-bit register → integrate into a 4-bit counter.

Greg outlined the transition from digital design to CPU design with a focus on sequential logic and state.
He contrasted combinational vs. sequential logic, highlighting that sequential circuits depend on stored state and a clock.
The class will construct a 4-bit counter using:
A 4-bit adder to compute next state.
A 4-bit register to hold state.
A clock signal to drive synchronous updates.
Greg noted that a new, LLM-friendly hardware description language is being finalized and will be introduced by Thursday.

The lesson progression covers: SR latch → D latch → multiplexer → D flip-flop.
Topics included:
Differences between static RAM and dynamic RAM.
SR latch structure, function, and intuitive behavior under various input conditions.

Behavior:
Demonstrated how an SR latch holds values through feedback.
Emphasized that hardware storage requires specific electrical states—unlike software memory writes.
Warned that S = 1 and R = 1 results in an undefined state and must be avoided.
Circuit:
Built the SR latch using NOR gates in the Digital tool and simulated its behavior.
Noted that the simulator may introduce non-determinism to reflect hardware realities; circuits should be initialized to a known state.
Identified ergonomic drawbacks: two-input setting semantics and potential for invalid inputs.

Design goals for improving the SR latch:
Accept a single data input.
Control when the value changes via a clock.
Eliminate undefined states.
Concepts introduced:
The clock signal (oscillation between low/high) to synchronize state changes.
The D latch, built by gating the SR latch with AND gates:
- When clock = 1: the latch is transparent and tracks the data input.
- When clock = 0: the latch holds its current value.

Greg implemented the D latch in the Digital tool:
Demonstrated that updates occur only when the clock is high.
Used input probes and a data graph to visualize timing and behavior.
A participant’s comment on similarities to CD data storage was briefly discussed and acknowledged.

Introduced the multiplexer as a combinational selector with multiple inputs and one output.
Implemented:
A 1-bit 2:1 MUX using AND/OR gates.
A 4-input MUX by composing 1-bit MUXes.
Discussed scaling:
Increasing bit width vs. composing smaller MUXes to manage complexity.

Compared approaches for building a 64-bit register:
Using 15 4-bit MUXes may be less performance-efficient but can be clearer from an abstraction and design perspective.
Brief digressions included run-length encoding, MP3/CD compression concepts, and a short personal note about a family trip to Oahu.
The session concluded with a plan to continue 4-bit register and counter implementation for an additional 30 minutes.

Explained an edge-triggered D flip-flop built from two D latches:
The first (master) latch captures input when clock = 0.
On the rising edge, the second (slave) latch stores the captured value.
The stored value is maintained for the full clock cycle; updates occur only on the next rising edge.

Implementation details:
Added clear and enable using multiplexers to control when the flip-flop updates.
Behavior:
- Updates occur only when both enable = 1 and the clock event occurs.
- Clear sets the output to 0.
Design guidance:
Avoid clock gating to prevent unintended state transitions.
Simulation note:
Current tooling does not expand D latches to base primitives during simulation; this capability is a goal for the Golden Gate toolchain.

Constructed a 4-bit register using splitters/mergers:
Connected shared clock, enable, and clear signals to all bits.
Built a 4-bit counter by:
Feeding the register’s output into a 4-bit adder (adding 1) and routing the sum back into the register input.
Lab plan:
Students will complete the flow from 1-bit full adder to 4-bit adder, then SR latch to 4-bit register, then integrate into a 4-bit counter by week’s end.
Next class:
Processor design will begin Thursday, building directly on the counter concepts.