Meeting Summary: CS 631-02 Systems Foundations¶

Quick Recap¶

Instructor Greg delivered a comprehensive introduction to digital design, covering:

Fundamentals of combinational logic, logic gates (AND, OR, NOT), and Boolean algebra.
Construction of a 1-bit full adder using the sum-of-products technique, extended to a 4-bit ripple-carry adder.
Core concepts in sequential logic, including latches and static RAM, and their role in building registers and stateful circuits.
How these components scale to larger designs such as counters—key elements in processor architecture.

Greg:
Send the lab assignment with instructions for downloading and using the digital design software. Due Thursday.
Continue Tuesday with sequential logic, latches, and larger circuits (including a 64-bit register and an n-bit counter).
Provide support for students experiencing issues running the Java digital design application, especially on macOS.
Students:
Complete the lightweight digital design lab (covering this session and the upcoming Tuesday session). Due Thursday.

The session began with combinational logic as a foundation before transitioning to sequential logic.
Although digital design is typically a two-semester sequence in electrical engineering, this module condensed essential concepts into one session.
The course progression to date includes C, Rust, RISC‑V assembly, and machine code; digital design extends this into computation with electrical circuits.

The discussion framed digital circuits as a subset of analog systems with discrete logic levels.
Schematic entry and graphical tools were introduced for design and simulation, with mention of physical construction using gates and wires.
References included the “NAND to Tetris” project and the use of FPGAs for rapid prototyping and reconfigurable hardware.

Differences between FPGAs and ASICs were highlighted: FPGAs offer flexibility but are slower; ASICs are faster but fixed-function. Both have become more accessible.
Prior student projects explored implementing custom processors on FPGAs.
Hardware Description Languages (HDLs) such as Verilog and VHDL were introduced, noting their steep learning curves. Greg is developing a new HDL emphasizing foundational concepts over complex tooling.
The session linked software concepts to digital hardware design, touching on circuit basics and power considerations.

Digital systems constrain continuous analog values to discrete ranges, producing binary outputs (0 or 1).
Logic gates—AND, OR, NOT—map cleanly to bitwise operators in languages like C and Rust.
Boolean algebra was introduced as a system with variables restricted to 0 or 1, alongside common notations.

Propositional logic notation and truth tables were used to illustrate AND, OR, and NOT behavior.
Only a few primitive gates are required to build a processor; the NAND gate is universal and can implement all others.
While a complete system can be constructed from NAND alone, using AND/OR/NOT improves clarity for learners building a CPU.

The session covered wiring and gate-level design, translating between Boolean expressions and circuit diagrams.
A practical goal was set: build a 4-bit adder.
Buses were introduced to represent multi-bit signals compactly in schematics.
A preview introduced the sum-of-products method for implementing arbitrary logic from truth tables.

Truth tables were constructed using binary counting.
The sum-of-products method:
Identify rows where the output is 1.
Form product terms by inverting inputs that are 0 in those rows.
OR the resulting product terms to form the final expression.
Implementation details included AND/OR/NOT usage, inversion via bubbles, and correct wire-junction notation.

A Java-based digital logic design tool was demonstrated, supporting circuit construction and simulation.
A simple OR-gate circuit was built and tested by toggling inputs and observing outputs.
Despite its older Java Swing UI, the tool effectively supports first-principles learning.

Greg described prior work on a gate-level RISC‑V processor and expressed confidence in reproducing it from memory.
Upcoming sessions will cover latches in depth, showing how they store values and form registers.
The sum-of-products technique was positioned as a bridge to building a full adder, then scaling to multi-bit designs.

A 1-bit full adder was designed from a truth table, deriving sum and carry-out product terms.
The circuit was implemented with AND/OR/NOT gates and packaged as a reusable component.
This design serves as the foundation for multi-bit addition.

Four 1-bit adders were chained by connecting each adder’s carry-out to the next adder’s carry-in.
Splitters and mergers handled multi-bit inputs and outputs.
The discussion introduced sequential logic and the need for registers; combinational logic was contrasted by its acyclic structure.

Cross-coupled NOR gates were used to create a basic bistable element, illustrating controlled feedback (cycles) in sequential logic.
The design functions as static RAM (SRAM), contrasted with dynamic RAM (DRAM).
Plans include building a 64-bit register and, later, larger systems like an n-bit counter with a clock, power, register, and adder.
A lab assignment will include instructions for the Java-based simulator.