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Meeting Summary: CS 631-01 Systems Foundations

  • Date: May 12, 2026
  • Time: 08:16 AM Pacific Time (US and Canada)
  • Meeting ID: 870 0988 0761

Quick Recap

The lecture focused on virtual memory and page tables, building on prior discussions of process isolation. Greg outlined three key components required for isolation: - Processor modes (kernel and user) - Interrupts, with emphasis on timer interrupts - Virtual memory and page tables

The session introduced multi-level page tables using a 32-bit, two-level example to reduce memory overhead, then transitioned to RISC-V’s three-level structure for 64-bit systems. The class concluded with an introduction to Project 6, which requires implementing a “track” command to monitor and collect performance metrics from user processes. Metrics include system calls, memory usage, and page table information. The project involves adding new system calls and extending the proc structure to indicate monitoring mode.

Next Steps

Greg

  • Post the GitHub link for Project 6 after class today.
  • Ensure the repository link is available before Thursday’s class.
  • On Thursday, answer questions and provide deeper kernel tracing examples, including page table walking and data structure manipulation.

Collaboration

  • All students: Review the Project 6 requirements and documentation before Thursday’s class.

Summary

Process Isolation and Page Tables

  • The lecture continued the process model for isolation, emphasizing three elements:
  • Processor modes control privilege (kernel vs. user).
  • Timer interrupts enable preemption and scheduling.
  • Virtual memory and page tables isolate address spaces across processes.
  • Discussion included how these mechanisms interact to allow concurrent execution while preventing unauthorized memory access.
  • Page table structures were reviewed:
  • A 32-bit, two-level page table reduces memory requirements relative to a single-level design.
  • RISC-V’s three-level page table supports 64-bit address spaces and efficient memory mapping.

Multi-Level Page Tables and Tracking

  • Multi-level page tables:
  • Covered the mechanics of page table walks performed by the processor.
  • Explained the role of translation caches (TLBs) in accelerating address translation.
  • Project 6: Tracking and metrics collection
  • Students must implement a “track” command that monitors:
    • System calls
    • Memory usage
    • Page table information
  • Required changes:
    • Add two system calls: TrackSelf and TrackWait.
    • Extend the proc structure with tracking capabilities (e.g., a flag or fields indicating monitoring mode and collected metrics).
  • The class discussed how to walk page tables in the kernel to classify memory and gather the necessary metrics.