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CS 631-01 Systems Foundations — Meeting Summary

  • Date: May 7, 2026
  • Time: 08:11 AM Pacific Time (US and Canada)
  • Meeting ID: 870 0988 0761

Quick Recap

The session focused on core operating systems concepts, specifically: - How processes run on a single core, with the kernel switching between them using timer interrupts and system calls. - Virtual memory fundamentals and multi-level page tables (L1 and L0) used to translate virtual addresses to physical addresses efficiently. - Memory efficiency concerns with large page tables and how sparse, multi-level designs mitigate excessive memory use. - Plans to continue with page tables in the next session, including coverage of the TLB (Translation Lookaside Buffer) and the RISC-V architecture.

Summary

Kernel Memory Management and Page Tables

  • The kernel manages memory using page tables that map virtual addresses to physical memory.
  • Each process has its own user page table, which includes restricted mappings for:
  • Code
  • Heap
  • Stack
  • A CPU register holds the active page table pointer; switching processes updates this pointer to enforce isolation and prevent unauthorized memory access.
  • Controlled inter-process data sharing is achieved through kernel-mediated mechanisms such as pipes and network sockets.
  • Page tables are organized as a multi-level structure (e.g., Level 1 → Level 0) to:
  • Enable sparse mappings.
  • Reduce memory overhead compared to flat page tables, especially on 32-bit systems.

Process Scheduling and Context Switching

  • Using Octox as an example, the discussion covered:
  • How the kernel performs context switches between processes on a single core.
  • The role of timer interrupts in preemption.
  • Scheduler context per core and how it coordinates process execution.
  • The session tied scheduling to virtual memory by explaining how the active page table changes on a context switch.
  • The meeting concluded with plans to continue page table implementation details and a reminder of the upcoming project deadline.

Next Steps

Greg

  • Post the final project assignment this week.

Collaboration and Deadlines

  • All students:
  • Continue and complete the current project due on Monday.
  • Reach out to Greg or Shreyas with questions.
  • Complete the final project by the last day of finals (as clarified by Greg in response to Aaron’s question).

Upcoming Topics

  • Deeper dive into page tables and their implementation.
  • TLB (Translation Lookaside Buffer).
  • RISC-V architecture.